View ICS853016_367654.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853016
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER
FEATURES
* (1) Differential 3.3V, 5V LVPECL / ECL output pair and (1) Single-ended 3.3V, 5V LVPECL / ECL output * (1) Differential D, nD input pair * D, nD pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Output frequency: >3GHz (typical) * Translates any single ended input signal to 3.3V to 5V LVPECL levels with resistor bias on nD input * Duty cycle skew: 10ps (typical) * Propagation delay: 400ps (typical) * LVPECL mode operating voltage supply range: VCC = 3.0V to 5.5V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -5.5V to -3.0V * -40C to 85C ambient operating temperature * Pin compatible with MC100EP16VCD and MC100EP16VCDT
GENERAL DESCRIPTION
The ICS853016 is a low skew, high performance 1-to-2 Differential-to-3.3V, 5V LVPECL/ HiPerClockSTM ECL Fanout Buffer and a member of the HiPerClockSTM family of High Perfor mance Clock Solutions from ICS. The ICS853016 is characterized to operate from either a 3.3V or a 5V power supply. Guaranteed duty cycle skew characteristic makes the ICS853016 ideal for those clock distribution applications demanding well defined performance and repeatability.
ICS
BLOCK DIAGRAM
nQ VCC
PIN ASSIGNMENT
nQ D VBB/nD nEN
1 2 3 4 8 7 6 5
Vcc QHG nQHG VEE
ICS853016
D QHG
8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View
VBB/nD
OE VBB LEN Q
nQHG
ICS853016
8-Lead TSSOP, 118mil 3mm x 3mm x 0.95mm package body G Package Top View
LATCH
nEN
D
VEE
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 853016AM www.icst.com/products/hiperclocks.html REV. A NOVEMBER 30, 2004
1
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853016
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER
Type Description Single-ended clock output. LVPECL interface levels. Pulldown Non-inver ting differential clock input. LVPECL interface levels. Reference voltage output/Inver ting differential clock input. LVPECL interface levels. Pulldown Enable input. Default LOW when left open. LVCMOS/LVTTL interface levels. Negative supply pin. Differential clock outputs. LVPECL interface levels. Positive supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6, 7 8 Name nQ D VBB/nD nEN VEE nQHG, QHG VCC Input Input Input Power Output Power Output
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN Parameter Input Pulldown Resistor Test Conditions Minimum Typical 75 Maximum Units K
853016AM
www.icst.com/products/hiperclocks.html
2
REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853016
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER
6V (LVPECL mode, VEE = 0) -6V (ECL mode, VCC = 0) -0.5V to VCC + 0.5V 0.5V to VEE - 0.5V 50mA 100mA 0.5mA -65C to 150C 112.7C/W (0 lfpm) 101.7C/W (0 m/s) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current VBB Sink/Source, IBB Storage Temperature, TSTG Package Thermal Impedance, JA Package Thermal Impedance, JA
Operating Temperature Range, TA -40C to +85C
(Junction-to-Ambient) for 8 Lead SOIC (Junction-to-Ambient) for 8 Lead TSSOP
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.0V TO 5.5V; VEE = 0V
Symbol VCC IE E Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.0 Typical 3.3 30 Maximum 5.5 Units V mA
TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol VOH VOL VIH VIL VBB VPP VCMR IIH Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage (Single-Ended) Input Low Voltage (Single-Ended) Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input High Current D Min
2.175 1.405 2.075 1.43 1.86 150 1.2 800
-40C Typ
2.275 1.545
Max
2.38 1.68 2.36 1.765 1.98 1200 3.3 150
Min
2.225 1.425 2.075 1.43 1.86 150 1.2
25C Typ
2.295 1.52
Max
2.37 1.615 2.36 1.765 1.98
Min
2.295 1.44 2.075 1.43 1.86 150 1.2
85C Typ
2.33 1.535
Max
2.365 1.63 2.36 1.765 1.98
Units
V V V V V
800
1200 3.3 150
800
1200 3.3 150
mV
V A A
-10 -10 IIL Input Low Current D Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for D is VCC + 0.3V.
-10
853016AM
www.icst.com/products/hiperclocks.html
3
REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853016
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER
-40C Typ
3.975 3.245
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 5.0V; VEE = 0V
Symbol VOH VOL VIH VIL VBB VPP VCMR IIH Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage (Single-Ended) Input Low Voltage (Single-Ended) Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input High Current D Min
3.875 3.105 3.775 3.13 3.56 150 1.2 800
Max
4.08 3.38 4.06 3.465 3.68 1200 5 150
Min
3.925 3.125 3.775 3.13 3.56 150 1.2
25C Typ
3.995 3.22
Max
4.07 3.315 4.06 3.465 3.68
Min
3.995 3.14 3.775 3.13 3.56 150 1. 2
85C Typ
4.03 3.235
Max
4.065 3.33 4.06 3.465 3.68
Units
V V V V V
800
1200 5 150
800
1200 5 150
mV
V A A
-10 -10 IIL Input Low Current D Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for D is VCC + 0.3V.
-10
TABLE 3D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.5V TO -3.0V
Symbol VOH VOL VIH VIL VBB VPP VCMR IIH Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input High Current D -40C Min
-1.125 -1.895 -1.225 -1.87 -1.44 150 VEE+1.2V 800
25C Max
-0.92 -1.62 -0.94 -1.535 -1.32 1200 0 150
85C Max
-0.93 -1.685 -0.94 -1.535 -1.32
Typ
-1.025 -1.755
Min
-1.075 -1.875 -1.225 -1.87 -1.44 150 VEE+1.2V
Typ
-1.005 -1.78
Min
-1.005 -1.86 -1.225 -1.87 -1.44 150 VEE+1.2V
Typ
-0.97 -1.765
Max
-0.935 -1.67 -0.94 -1.535 -1.32
Units
V V V V V
800
1200 0 150
800
1200 0 150
mV
V A A
-10 -10 IIL Input Low Current D Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for D is VCC + 0.3V.
-10
853016AM
www.icst.com/products/hiperclocks.html
4
REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853016
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER
OR
TABLE 4. AC CHARACTERISTICS, VCC = 0V; VEE = -5.5V TO -3.0V
Symbol fMAX Parameter Output Frequency (Differential) nQ Propagation Delay; NOTE 1 (Differential) QHG, nQHG (Single-Ended) nQ (Single-Ended) QHG, nQHG Min
VCC = 3.0V TO 5.5V; VEE = 0V
25C Max Min Typ >3 35 0 400 400 450 10 30 0 150 Max Min 85C Typ TBD TBD TBD TBD TBD TBD TBD TBD Max Units GHz ps ps ps ps ps ps ps
-40C Typ TBD TBD TBD TBD TBD TBD TBD TBD
tPLH tPHL tsk(odc)
tR/tF
Duty Cycle Skew; NOTE 2, 3 Output Rise/ nQ Fall Time 20% to 80% QHG, nQHG
All parameters are measured at f 1.7GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured for only differential operation from the cross point of the inputs to the cross point of the outputs. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
853016AM
www.icst.com/products/hiperclocks.html
5
REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853016
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
SCOPE
VCC
nQHG
LVPECL
nQx QHG
V
PP
Cross Points
V
CMR
VEE
V EE
-3.5V to -1.0V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nD D
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
nQ nQHG QHG tpLH
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
Part 1 nQHG QHG Part 2 nQHG QHG
tsk(odc)
DUTY CYCLE SKEW
853016AM
www.icst.com/products/hiperclocks.html
6
REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853016
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
Figure 1 shows an example of the input that can be wired to accept single ended LVPECL levels.
VCC
C1 0.1u
CLK_IN
D
VBB/nD
FIGURE 1. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
853016AM
www.icst.com/products/hiperclocks.html
7
REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853016
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
Zo = 50 84 84
1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
TERMINATION FOR 5V LVPECL OUTPUT
This section shows examples of 5V LVPECL output termination. Figure 3A shows standard termination for 5V LVPECL. The termination requires matched load of 50 resistors pull down to
VCC - 2V = 3V at the receiver. Figure 3B shows Thevenin equivalence of Figure 3A. In actual application where the 3V DC power supply is not available, this approached is normally used.
5V
5V
5V
5V
R3 84
R4 84
+
PECL
Zo = 50 Ohm
PECL
Zo = 50 Ohm
+
Zo = 50 Ohm
Zo = 50 Ohm
-
PECL
R1 125
-
PECL
R1 50
3V
R2 50
R2 125
FIGURE 3A. STANDARD 5V PECL OUTPUT TERMINATION
FIGURE 3B. 5V PECL OUTPUT TERMINATION EXAMPLE
853016AM
www.icst.com/products/hiperclocks.html
8
REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853016
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853016. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS853016 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 5.5V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 5.5V * 30mA = 165mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW
Total Power_MAX (3.8V, with all outputs switching) = 165mW + 61.88mW = 226.88mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5A below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.227W * 103.3C/W = 108.4C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 5A. THERMAL RESISTANCE JA
FOR
8-PIN SOIC, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 5B. THERMAL RESISTANCE JA
FOR
8-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards
853016AM
1
90.5C/W
2
89.8C/W
REV. A NOVEMBER 30, 2004
101.7C/W
www.icst.com/products/hiperclocks.html
9
PRELIMINARY
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 4.
ICS853016
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER
VCC
Q1
VOUT
RL
50 VCC - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 0.935V
-V
OH_MAX
) = 0.935V =V - 1.67V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.67V
Pd_H = [(V
OH_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC _MAX
-V
OH_MAX
)=
[(2V - 0.935V)/50] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
853016AM
www.icst.com/products/hiperclocks.html
10
REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853016
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6A.
JAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0 200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
153.3C/W 112.7C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6B. JAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2
89.8C/W
TRANSISTOR COUNT
The transistor count for ICS853016 is: 163
853016AM
www.icst.com/products/hiperclocks.html
11
REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853016
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 7A. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
TABLE 7B. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e e1 L aaa 0.40 0 --0 0.79 0.22 0.08 3.00 BASIC 4.90 BASIC 3.00 BASIC 0.65 BASIC 1.95 BASIC 0.80 8 0.10 Millimeters Minimum 8 1.10 0.15 0.97 0.38 0.23 Maximum
Reference Document: JEDEC Publication 95, MS-012
Reference Document: JEDEC Publication 95, MO-187
853016AM
www.icst.com/products/hiperclocks.html
12
REV. A NOVEMBER 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853016
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER
Package 8 lead SOIC 8 lead SOIC on Tape and Reel 8 lead TSSOP 8 lead TSSOP on Tape and Reel Count 96 per tube 2500 100 per tube 2500 Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS853016AM ICS853016AMT ICS853016AG ICS853016AGT Marking 853016A 853016A 016A 016A
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853016AM
www.icst.com/products/hiperclocks.html
13
REV. A NOVEMBER 30, 2004

▲Up To Search▲

Price & Availability of ICS853016

	To Download ICS853016 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .